Different computer systems may process information utilizing different data formats. In the most typical case, the computer receives data, for example an 8-bit data word A.sub.0 -A.sub.7, in serial format with bit A.sub.0 being received first, followed in sequence by bits A.sub.1 through A.sub.7. Computer systems are available, however, that receive the data A.sub.0 -A.sub.7 in a reverse or "flipped" format. That is, bit A.sub.7 is received first, followed in sequence by bits A.sub.6 through A.sub.0. For example, IBM 5250 systems utilize the former protocol wherein data is received in the A.sub.0 -A.sub.7 sequential format. On the other hand, IBM 3270/3299 systems utilize the latter "flipped" protocol wherein data is received in the A.sub.7 -A.sub.0 sequential format.
Thus, if a single transmitter architecture is to be used for transmitting data bytes to both normal and "flipped" protocol systems, then the transmitter must have the internal capability to "flip" the data end for end.
To accomplish this, the present invention provides a transfer gate two-to-one multiplexer at the data input to a shift register under transmitter control. This allows for multi-protocol transmitter operation without the need for two distinct transmitter units.
Previously, this type of operational capability required multiple chip solutions. However, the system time constraints for multi-function, high speed applications require the innovative approach provided by the present invention.